Çiçek, İhsanAl Khas, Ahmad2022-02-072022-02-072022Cicek, I., & Al Khas, A. (2022). A new read–write collision-based SRAM PUF implemented on xilinx FPGAs. Journal of Cryptographic Engineering, doi:10.1007/s13389-021-00281-82190-8508https://doi.org/10.1007/s13389-021-00281-8https://hdl.handle.net/20.500.12713/2467Physically unclonable functions (PUFs) are device-specific digital fingerprints derived from physical properties. They are used in critical cryptographic applications, including unique ID generation, key generation, and challenge-response-based authentication. The advantages of low implementation cost and robust operation render PUF an indispensable component for secure embedded systems. In the last decade, SRAM-based PUFs have become very popular in the ASIC industry due to increasing security demand against cloning and counterfeiting. However, their use in the FPGA applications is limited, since it is almost impossible to power-cycle the SRAMs after the FPGA device is configured. Additionally, FPGA vendors usually clear the SRAM contents after power on which also makes it hard to implement an SRAM PUF. In this work, we propose a new approach for designing SRAM-based PUFs on Xilinx FPGAs. The proposed PUF is based on the idea of triggering a collision between reading and writing operations in a block-RAM to generate random responses induced by timing violation instead of power cycling. We have integrated the proposed PUF as an AXI peripheral with a synthesizable processor core for data acquisition. The design has been tested on 10 different Xilinx Artix-7 devices of the same type, and acquired data were tested for reliability, uniqueness, bit-aliasing, and uniformity properties. On the average, the proposed PUF achieved 93% reliability (at 55 ?C), 37% uniqueness, 47% bit-aliasing, and 55% uniformity. © 2021, The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature.eninfo:eu-repo/semantics/closedAccessCryptographic PrimitiveFPGAPhysically Unclonable FunctionPUFRead–write CollisionSRAM PUFA new read–write collision-based SRAM PUF implemented on Xilinx FPGAsArticleWOS:0007481586000012-s2.0-85123869777Q210.1007/s13389-021-00281-8Q2