FFT-based McLaughlin's montgomery exponentiation without conditional selections

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dc.authoridÇetin Kaya Koç / 0000-0002-2572-9565
dc.authorscopusidÇetin Kaya Koç / 57053693300
dc.authorwosidÇetin Kaya Koç / GBX-7437-2022
dc.authorwosidÇetin Kaya Koç / W-3929-2018 wos
dc.contributor.authorDai, Wangchen
dc.contributor.authorChen, Donglong
dc.contributor.authorCheung, Ray C.C.
dc.contributor.authorKoç, Çetin Kaya
dc.date.accessioned2020-08-30T20:01:38Z
dc.date.available2020-08-30T20:01:38Z
dc.date.issued2018
dc.departmentİstinye Üniversitesi, Mühendislik ve Doğa Bilimleri Fakültesi, Bilgisayar Mühendisliği Bölümüen_US
dc.descriptionKoç, Çetin Kaya ( isu author)
dc.description.abstractModular multiplication forms the basis of many cryptographic functions such as RSA, Diffie-Hellman key exchange, and ElGamal encryption. For large RSA moduli, combining the fast Fourier transform (FFT) with McLaughlin's Montgomery modular multiplication (MLM) has been validated to offer cost-effective implementation results. However, the conditional selections in McLaughlin's algorithm are considered to be inefficient and vulnerable to timing attacks, since extra long additions or subtractions may take place and the running time of MLM varies. In this work, we restrict the parameters of MLM by a set of new bounds and present a modified MLM algorithm involving no conditional selection. Compared to the original MLM algorithm, we inhibit extra operations caused by the conditional selections and accomplish constant running time for modular multiplications with different inputs. As a result, we improve both area-time efficiency and security against timing attacks. Based on the proposed algorithm, efficient FFT-based modular multiplication and exponentiation are derived. Exponentiation architectures with dual FFT-based multipliers are designed obtaining area-latency efficient solutions. The results show that our work offers a better efficiency compared to the state-of-the-art works from and above 2048-bit operand sizes. For single FFT-based modular multiplication, we have achieved constant running time and obtained area-latency efficiency improvements up to 24.3 percent for 1,024-bit and 35.5 percent for 4,096-bit operands, respectively. © 2012 IEEE.en_US
dc.description.sponsorshipThe authors would like to thank the anonymous reviewers for their valuable comments and suggestions to improve the quality of the paper. They are also grateful to Mr. Jingwei Hu who contributed the key ideas on side-channel analysis. This work was supported by the Research Grant Council of the Hong Kong Special Administrative Region, China (Project No. CityU 111913) and Croucher Statup Allowance, 9500015.en_US
dc.identifier.citationDai, W., Chen, D., Cheung, R. C., & Koç, Ç. K. (2018). FFT-Based McLaughlin's Montgomery Exponentiation without Conditional Selections. IEEE Transactions on Computers, 67(9), 1301-1314.en_US
dc.identifier.doi10.1109/TC.2018.2811466en_US
dc.identifier.endpage1314en_US
dc.identifier.issn0018-9340en_US
dc.identifier.issue9en_US
dc.identifier.scopus2-s2.0-85043396379en_US
dc.identifier.scopusqualityQ1en_US
dc.identifier.startpage1301en_US
dc.identifier.urihttps://doi.org/10.1109/TC.2018.2811466
dc.identifier.urihttps://hdl.handle.net/20.500.12713/333
dc.identifier.volume67en_US
dc.indekslendigikaynakScopusen_US
dc.institutionauthorKoç, Çetin Kayaen_US
dc.language.isoenen_US
dc.publisherIEEE Computer Societyen_US
dc.relation.ispartofIEEE Transactions on Computersen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectField-Programmable Gate Array (Fpga)en_US
dc.subjectModular Exponentiationen_US
dc.subjectMontgomery Modular Multiplicationen_US
dc.subjectNumber-Theoretic Weighted Transformen_US
dc.subjectRsa Encryptionen_US
dc.titleFFT-based McLaughlin's montgomery exponentiation without conditional selectionsen_US
dc.typeArticleen_US

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