Field-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processor

dc.authoridİhsan Çiçek / 0000-0002-7881-1263
dc.authorscopusidİhsan Çiçek / 55789978000
dc.authorwosidİhsan Çiçek / JMW-4819-2023
dc.contributor.authorKashif, Muhammad
dc.contributor.authorÇiçek, İhsan
dc.date.accessioned2021-08-10T06:50:33Z
dc.date.available2021-08-10T06:50:33Z
dc.date.issued2021en_US
dc.departmentİstinye Üniversitesi, Mühendislik ve Doğa Bilimleri Fakültesi, Elektrik-Elektronik Bölümüen_US
dc.description.abstractElliptic curve cryptography provides a widely recognized secure environment for information exchange in resource-constrained embedded system applications, such as Internet-of-Things, wireless sensor networks, and radio frequency identification. As the elliptic-curve cryptography (ECC) arithmetic is computationally very complex, there is a need for dedicated hardware for efficient computation of the ECC algorithm in which scalar point multiplication is the performance bottleneck. In this work, we present an ECC accelerator that computes the scalar point multiplication for the NIST recommended elliptic curves over Galois binary fields by using a polynomial basis. We used the Montgomery algorithm with projective coordinates for the scalar point multiplication. We designed a hybrid finite field multiplier based on the standard Karatsuba and shift-and-add multiplication algorithms that achieve one finite field multiplication in m2 clock cycles for a key-length of m. The proposed design has been modeled in Verilog hardware description language (HDL), functionally verified with simulations, and implemented for field-programmable gate array (FPGA) devices using vendor tools to demonstrate hardware efficiency. Finally, we have integrated the ECC accelerator as an AXI4 peripheral with a synthesizable microprocessor on an FPGA device to create an elliptic curve crypto-processor.en_US
dc.identifier.citationKASHIF, M., & ÇİÇEK, İ. (2021). Field-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processor. Turkish Journal of Electrical Engineering & Computer Sciences, 29(4), 2127-2139.en_US
dc.identifier.doi10.3906/elk-2008-8en_US
dc.identifier.endpage2139en_US
dc.identifier.issn1300-0632en_US
dc.identifier.issn1303-6203en_US
dc.identifier.issue4en_US
dc.identifier.scopus2-s2.0-85112711361en_US
dc.identifier.scopusqualityQ3en_US
dc.identifier.startpage2127en_US
dc.identifier.trdizinid524068en_US
dc.identifier.urihttps://doi.org/10.3906/elk-2008-8
dc.identifier.urihttps://hdl.handle.net/20.500.12713/1993
dc.identifier.volume29en_US
dc.identifier.wosWOS:000679322900006en_US
dc.identifier.wosqualityQ4en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.indekslendigikaynakTR-Dizinen_US
dc.institutionauthorÇiçek, İhsan
dc.language.isoenen_US
dc.publisherTUBITAK SCIENTIFIC & TECHNICAL RESEARCH COUNCIL TURKEYen_US
dc.relation.ispartofTURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCESen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectElliptic Curve Cryptographyen_US
dc.subjectKaratsuba Multiplieren_US
dc.subjectCrypto-Acceleratoren_US
dc.subjectCrypto-Processoren_US
dc.subjectScalar Multiplica-Tionen_US
dc.subjectField-Programmable Gate Arrayen_US
dc.titleField-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processoren_US
dc.typeArticleen_US

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