A new read–write collision-based SRAM PUF implemented on Xilinx FPGAs

dc.authoridİhsan Çiçek / 0000-0002-7881-1263en_US
dc.authoridAhmad El Khas / 0000-0003-1005-5868
dc.authorscopusidAhmad El Khas / 57215419803
dc.authorscopusidİhsan Çiçek / 55789978000
dc.authorwosidAhmad El Khas / AFG-8330-2022
dc.authorwosidİhsan Çiçek / V-5477-2017
dc.contributor.authorÇiçek, İhsan
dc.contributor.authorAl Khas, Ahmad
dc.date.accessioned2022-02-07T08:29:05Z
dc.date.available2022-02-07T08:29:05Z
dc.date.issued2022en_US
dc.departmentİstinye Üniversitesi, Mühendislik ve Doğa Bilimleri Fakültesi, Elektrik-Elektronik Bölümüen_US
dc.description.abstractPhysically unclonable functions (PUFs) are device-specific digital fingerprints derived from physical properties. They are used in critical cryptographic applications, including unique ID generation, key generation, and challenge-response-based authentication. The advantages of low implementation cost and robust operation render PUF an indispensable component for secure embedded systems. In the last decade, SRAM-based PUFs have become very popular in the ASIC industry due to increasing security demand against cloning and counterfeiting. However, their use in the FPGA applications is limited, since it is almost impossible to power-cycle the SRAMs after the FPGA device is configured. Additionally, FPGA vendors usually clear the SRAM contents after power on which also makes it hard to implement an SRAM PUF. In this work, we propose a new approach for designing SRAM-based PUFs on Xilinx FPGAs. The proposed PUF is based on the idea of triggering a collision between reading and writing operations in a block-RAM to generate random responses induced by timing violation instead of power cycling. We have integrated the proposed PUF as an AXI peripheral with a synthesizable processor core for data acquisition. The design has been tested on 10 different Xilinx Artix-7 devices of the same type, and acquired data were tested for reliability, uniqueness, bit-aliasing, and uniformity properties. On the average, the proposed PUF achieved 93% reliability (at 55 ?C), 37% uniqueness, 47% bit-aliasing, and 55% uniformity. © 2021, The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature.en_US
dc.identifier.citationCicek, I., & Al Khas, A. (2022). A new read–write collision-based SRAM PUF implemented on xilinx FPGAs. Journal of Cryptographic Engineering, doi:10.1007/s13389-021-00281-8en_US
dc.identifier.doi10.1007/s13389-021-00281-8en_US
dc.identifier.issn2190-8508en_US
dc.identifier.scopus2-s2.0-85123869777en_US
dc.identifier.scopusqualityQ2en_US
dc.identifier.urihttps://doi.org/10.1007/s13389-021-00281-8
dc.identifier.urihttps://hdl.handle.net/20.500.12713/2467
dc.identifier.wosWOS:000748158600001en_US
dc.identifier.wosqualityQ2en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.institutionauthorÇiçek, İhsan
dc.institutionauthorAl Khas, Ahmad
dc.language.isoenen_US
dc.publisherSpringer Science and Business Media Deutschland GmbHen_US
dc.relation.ispartofJournal of Cryptographic Engineeringen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectCryptographic Primitiveen_US
dc.subjectFPGAen_US
dc.subjectPhysically Unclonable Functionen_US
dc.subjectPUFen_US
dc.subjectRead–write Collisionen_US
dc.subjectSRAM PUFen_US
dc.titleA new read–write collision-based SRAM PUF implemented on Xilinx FPGAsen_US
dc.typeArticleen_US

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